SmartCell Architecture, Design and Performance Analysis for Reconfigurable Embedded Computing
نویسنده
چکیده
This abstract presents SmartCell, a coarse-grained reconfigurable architecture, which tiles a large number of computing units with flexible interconnection fabrics on a single chip. SmartCell is a highly evolvable system in the sense that the number of processing units can be dynamically changed to adapt to different system requirements. It can also be configured to operate in various computing styles such as SIMD, MIMD and systolic array fashions. After discussing about the fundamental features, the design of a seedling SmartCell system with 64 processor elements is presented. The simulation results show that on average SmartCell is about 2 and 5 times more power efficient than the RaPiD and Stratix II FPGA, respectively.
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